The state-of-the-art III-V semiconductor power devices, such as pHEMT (pseudomorphic high-electron mobility transistor) devices or HBT (Heterojunction Bipolar Transistor) devices, require not only sophisticated fabrication processes on the front-side of a semiconductor wafer, but also back-side wafer processing, such as via-hole etching and metal coating.
For back-side via-hole processing, the wafer has to be thinned to a desired thickness, which is typically less than 100 μm. An important step in back-side processing of GaAs wafers for power devices is the deposition of metal layer on the back-side surface and into through substrate via holes in order to meet thermal conduction requirements and provide low inductance ground connections. During the back-side wafer processing steps, the wafers front-sides were mounted onto flat carriers. To prevent possible damages to the front-side devices, the fabricated devices must be carefully protected or passivated. However, the processing steps will be further complicated if the front-side wafer requires bumping processes. Typical bumping processes will lead to a surface topological difference of about 50-100 μm. If the front-side bumping processes were proceeded before wafer thinning for back-side processing, it becomes very difficult to protect the surface bumps of such a large topological difference when attaching the wafer front side to the carrier substrate.
A possible approach is to perform back-side wafer processing steps prior to the surface bumping processes. However, the major technical challenge is that the wafer will become highly brittle after wafer thinning. Wafers were usually damaged, or even cracked during further processing steps for front side devices. Therefore, it is necessary to develop a method for handling thinned wafer, which can sustain further processing, such as thermal treatments and/or chemical etchings.